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A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.

Taegeun YooHyunjoon KimQian ChenTony Tae-Hyoung KimBongjin Kim
Published in: ISLPED (2019)
Keyphrases
  • random access memory
  • embedded dram
  • neural network
  • design considerations
  • low voltage
  • memory access
  • dynamic random access memory
  • main memory
  • low cost
  • cmos technology
  • real time
  • data structure
  • parallel computation