Qian Chen

Publication Activity (10 Years)

Years Active: 2019-2023
Publications (10 Years): 11

Top Topics

Random Access Memory

Design Considerations

Top Venues

Publications

Qian Chen, Chirn Chye Boon, Qing Liu, Yuan Liang
A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS. IEEE J. Solid State Circuits 58 (6) (2023)
Qian Chen, Chirn Chye Boon, Yuan Liang
A 0.6 V 4 GS/s -56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS. IEEE Access 10 (2022)
Yuan Liang, Chirn Chye Boon, Qian Chen, Yangtao Dong
Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer. ISCAS (2021)
Qian Chen, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu, Ting Guo
Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line. ISCAS (2020)
Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length. DATE (2020)
Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. ISCAS (2020)
Qian Chen, Yuan Liang, Chirn Chye Boon
A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS. ISCAS (2020)
Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks. ISOCC (2019)
Taegeun Yoo, Hyunjoon Kim, Qian Chen, Tony Tae-Hyoung Kim, Bongjin Kim
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. ISLPED (2019)
Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation. ESSCIRC (2019)
Hyunjoon Kim, Qian Chen, Bongjin Kim
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC. A-SSCC (2019)