Design and Verification of Cache Memory Decoder for High Speed Multicore Processor.

A. Ravi Kumar Cyril Prasanna Raj G. M. Sree Rama Reddy

Published in: ICETET (2010)

Keyphrases

high speed
memory hierarchy
memory management
functional verification
memory subsystem
memory access
single chip
computing power
operating system
low power
main memory
computer architecture
cache misses
external memory
high end
prefetching
data access
processor core
model checking