A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.
Ehsan AtoofianZainalabedin NavabiPublished in: Asian Test Symposium (2003)
Keyphrases
- hardware implementation
- hardware architecture
- real time
- software implementation
- hardware design
- fpga implementation
- dedicated hardware
- fpga technology
- hardware architectures
- pipelined architecture
- low cost
- systolic array
- signal processing
- test cases
- xilinx virtex
- fpga device
- hardware software co design
- reconfigurable hardware
- real time image processing
- parallel architecture
- field programmable gate array
- high speed
- neural network
- parallel hardware
- efficient implementation
- case study
- data sets