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Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET.

Chang XueYihan ZhangPeiyu ChenMingwei ZhuTianqiao WuMeng WuYandong HeLe Ye
Published in: ISCAS (2022)
Keyphrases
  • high speed
  • cmos technology
  • digital circuits
  • circuit design
  • electronic circuits
  • read write
  • delay insensitive
  • design considerations
  • improved algorithm
  • analog circuits
  • duty cycle