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On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.
Ashesh Rastogi
Wei Chen
Sandip Kundu
Published in:
DAC (2007)
Keyphrases
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leakage current
low voltage
cmos technology
power line
random access memory
design considerations
power consumption
low power
power management
analog vlsi
high speed
cost effective
parallel processing
power dissipation
real time
negative impact
power reduction
delay insensitive
electrical properties