Multi-standard low-power DDR I/O circuit design in 7nm CMOS process.
Moo Sung ChaeTom WilsonEric NaviaskyPublished in: ISCAS (2017)
Keyphrases
- low power
- circuit design
- power consumption
- high speed
- low cost
- cmos technology
- high power
- single chip
- power reduction
- vlsi circuits
- digital signal processing
- nm technology
- design automation
- input output
- low power consumption
- wireless transmission
- gate array
- vlsi architecture
- power saving
- low voltage
- digital circuits
- mixed signal
- logic circuits
- power dissipation
- image sensor
- video sequences
- image processing
- real time