Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.
Danghui WangXiaoya FanDeyuan GaoShengbing ZhangJianfeng AnPublished in: ICESS (2005)
Keyphrases
- high speed
- physical design
- floating point arithmetic
- circuit design
- functional verification
- built in self test
- scheduling problem
- ibm power processor
- parallel implementation
- floating point
- scheduling algorithm
- analog vlsi
- chip design
- parallel computing
- massively parallel
- design methodology
- memory subsystem
- multithreading
- instruction set
- low cost
- level parallelism
- real time
- vlsi implementation
- distributed memory
- computer architecture
- ibm zenterprise
- processor core
- single chip
- general purpose