Precise error determination of approximated components in sequential circuits with model checking.
Arun ChandrasekharanMathias SoekenDaniel GroßeRolf DrechslerPublished in: DAC (2016)
Keyphrases
- model checking
- temporal logic
- asynchronous circuits
- formal verification
- finite state machines
- temporal properties
- formal specification
- finite state
- symbolic model checking
- model checker
- verification method
- process algebra
- transition systems
- automated verification
- reachability analysis
- computation tree logic
- partial order reduction
- pspace complete
- epistemic logic
- formal methods
- concurrent systems
- bounded model checking
- timed automata
- linear temporal logic
- software components
- abstract interpretation
- linear time temporal logic