A BDD-based verification method for large synthesized circuits.
C. A. J. van EijkPublished in: Integr. (1997)
Keyphrases
- verification method
- model checking
- temporal logic
- binary decision diagrams
- delay insensitive
- high speed
- asynchronous circuits
- heuristic search algorithms
- digital circuits
- analog circuits
- breadth first search
- circuit design
- high level synthesis
- vlsi circuits
- information systems
- lateral inhibition
- power reduction
- set bounds propagation
- logic synthesis
- tunnel diode
- data sets
- logic circuits
- heuristic search
- lower bound
- data structure
- search engine
- artificial intelligence
- data mining
- real world
- neural network