C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration.
Xiaoyun Li
Houpeng Chen
Qian Wang
Xi Li
Yu Lei
Qi Zhang
Xi Fan
Jiajun Hu
Zhen Tian
Zhitang Song
Published in:
IEICE Electron. Express (2017)
Keyphrases
</>
high speed
circuit design
analog circuits
tunnel diode
power reduction
parallel processing
database
evolvable hardware
logic circuits
optimal configuration
digital circuits
electronic circuits
low voltage
decision support
low cost
web services
real time