An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS.
Ryota SekimotoAkira ShikataKentaro YoshiokaTadahiro KurodaHiroki IshikuroPublished in: IEICE Trans. Electron. (2013)
Keyphrases
- low voltage
- cmos technology
- low power
- high speed
- leakage current
- power line
- design considerations
- single chip
- random access memory
- power consumption
- silicon on insulator
- synthetic aperture radar
- low cost
- sar images
- parallel processing
- mixed signal
- delay insensitive
- image sensor
- power dissipation
- analog to digital converter
- digital signal processing
- power management
- image enhancement
- multi view
- computer vision