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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology.

Ming-Dou KerKun-Hsien Lin
Published in: IEEE J. Solid State Circuits (2005)
Keyphrases
  • power consumption
  • cmos technology
  • power dissipation
  • low power
  • input output
  • design process
  • embedded systems
  • cmos image sensor
  • ibm power processor
  • single chip
  • power management
  • spl times
  • silicon on insulator