Architecture of built-in self-test and recovery memory chips.
V. A. AndrienkoMoamar DiaaV. G. RyabtsevTetyana UtkinaPublished in: EWDTS (2013)
Keyphrases
- processing elements
- digital signal processors
- integrated circuit
- high speed
- management system
- memory management
- computing power
- built in self test
- network architecture
- associative memory
- event driven
- hardware implementation
- memory usage
- real time
- recovery algorithm
- memory requirements
- neural network
- computer systems
- level parallelism
- memory size
- multithreading
- software architecture
- communication protocol
- error detection
- limited memory
- design considerations
- massively parallel