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Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.

Yohei HasegawaShohei AbeKatsuaki DeguchiMasayasu SuzukiHideharu Amano
Published in: FPGA (2005)
Keyphrases
  • evaluation process
  • neural network
  • total cost
  • high cost
  • testing process
  • search algorithm
  • high speed
  • parallel processing
  • cost sensitive
  • evaluation measures
  • evaluation metrics
  • high end
  • cost reduction