A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit.
Sharad GuptaParvinder Kumar RanaPublished in: ISOCC (2012)
Keyphrases
- cmos technology
- power consumption
- dynamic random access memory
- power reduction
- power dissipation
- low power
- random access memory
- embedded dram
- nm technology
- high speed
- low voltage
- level parallelism
- leakage current
- programming language
- silicon on insulator
- peer to peer
- fault tolerance
- memory requirements
- main memory
- circuit design
- memory subsystem
- parallel processing
- load balancing
- software systems
- computational power
- low cost