Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
Snaider CarrilloJim HarkinLiam McDaidFearghal MorganSandeep PandeSeamus CawleyBrian McGinleyPublished in: IEEE Trans. Parallel Distributed Syst. (2013)
Keyphrases
- network on chip
- multi processor
- spiking neural networks
- routing algorithm
- biologically inspired
- packet switched
- network simulator
- neural network
- real time
- cerebellar model
- network architecture
- data flow
- multi core processors
- program execution
- liquid state machine
- shared memory
- routing protocol
- high speed
- low cost
- image processing