A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC.
Shunsuke OkuraTetsuro OkuraIndika U. K. Bogoda AppuhamylageKenji TaniguchiPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2007)
Keyphrases
- low power
- energy efficient
- power consumption
- energy efficiency
- single chip
- low cost
- high speed
- power dissipation
- wireless sensor networks
- flip flops
- multi core architecture
- sensor networks
- energy consumption
- analog to digital converter
- cmos technology
- real time
- digital signal processing
- image processing
- power reduction
- master slave
- mixed signal
- massively parallel