Low Power Scan Chain Architecture Based on Circuit Topology.
Heetae KimHyunggoy OhSangjun LeeSungho KangPublished in: ISOCC (2018)
Keyphrases
- low power
- cmos technology
- high speed
- vlsi architecture
- power consumption
- logic circuits
- nm technology
- low cost
- mixed signal
- gate array
- vlsi circuits
- power reduction
- power dissipation
- single chip
- delay insensitive
- low voltage
- wireless transmission
- digital signal processing
- high power
- low power consumption
- real time
- parallel processing
- energy dissipation
- image sensor
- power management
- signal processing