A DRAM/SRAM Memory Scheme for Fast Packet Buffers.

Jorge García-Vidal Maribel March Llorenç Cerdà Jesús Corbal Mateo Valero

Published in: IEEE Trans. Computers (2006)

Keyphrases

dynamic random access memory
main memory
embedded dram
random access memory
low voltage
buffer size
power consumption
packet size
external memory
bloom filter
memory subsystem
data structure
memory space
random access
data transmission
production system
database management systems