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Using Hard Macros to Reduce FPGA Compilation Time.

Christopher LavinMarc PadillaSubhrashankha GhoshBrent E. NelsonBrad L. HutchingsMichael J. Wirthlin
Published in: FPL (2010)
Keyphrases
  • high speed
  • real time
  • hardware implementation
  • hardware design
  • real time image processing
  • source code
  • significantly reduced
  • image processing
  • signal processing
  • data acquisition
  • key features