A low-power pseudo-dynamic full adder cell for image addition.

Ayoub Sadeghi Nabiollah Shiri Mahmood Rafiee Parisa Rahimi

Published in: Comput. Electr. Eng. (2020)

Keyphrases

low power
power consumption
low cost
high speed
logic circuits
power dissipation
vlsi circuits
edge detection
high power
data flow
error correction
delay insensitive
single chip
jpeg images
high resolution
pixel values
digital images