A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology.
Hongming ChenYuhua ChengPublished in: Sci. China Inf. Sci. (2014)
Keyphrases
- low voltage
- leakage current
- cmos technology
- random access memory
- low power
- image sensor
- power consumption
- power line
- parallel processing
- design considerations
- edge detection
- low cost
- image processing algorithms
- dynamic range
- high speed
- power dissipation
- embedded dram
- real time
- hardware and software
- multi view
- computer vision