Hybrid on-line self-test architecture for computational units on embedded processor cores.
Andrea FloridiaGianmarco MonganoDavide PiumattiErnesto SánchezPublished in: DDECS (2019)
Keyphrases
- level parallelism
- multi core processors
- dynamic random access memory
- multi processor
- parallel architecture
- processing units
- instruction set
- embedded processors
- computation intensive
- hardware software
- neural network
- industry standard
- real time
- general purpose
- multi core architecture
- central processing unit
- systolic array
- processor core
- management system
- embedded systems
- test cases
- smart camera
- processing elements
- parallel architectures
- memory hierarchy
- single chip
- computational power
- data flow
- hardware implementation
- parallel processing
- multi core systems
- general purpose processors
- power consumption