Stall Power Reduction in Pipelined Architecture Processors.
Pejman Lotfi-KamranAmir-Mohammad RahmaniAli-Asghar SalehpourAli Afzali-KushaZainalabedin NavabiPublished in: VLSI Design (2008)
Keyphrases
- power reduction
- pipelined architecture
- power consumption
- multithreading
- low power
- field programmable gate array
- parallel computing
- power saving
- hardware implementation
- power dissipation
- energy efficiency
- parallel algorithm
- highly efficient
- computer vision
- energy saving
- parallel processing
- low cost
- high speed
- case study
- multi threaded
- multi core processors
- memory efficient
- wireless networks
- high performance computing