An inter-FPGA communication bus with error detection and dynamic clock phase adjustment.
Lucas T. MeloS. H. C. SantanaAbel G. Silva-FilhoManoel Eusebio de LimaVictor Wanderley Costa de MedeirosMarcelo L. M. MarinhoPublished in: J. Braz. Comput. Soc. (2015)
Keyphrases
- error detection
- high speed
- error correction
- fault isolation
- data acquisition
- data cleansing
- dynamic environments
- power consumption
- fault tolerance
- error recovery
- artificial intelligence
- communication systems
- low power
- neural network
- hardware implementation
- error resilient
- error correcting
- low cost
- diagnostic tests
- fpga device