FPGA clock network architecture: flexibility vs. area and power.
Julien LamoureuxSteven J. E. WiltonPublished in: FPGA (2006)
Keyphrases
- network architecture
- power consumption
- high speed
- artificial neural
- power reduction
- neural network
- duty cycle
- neural network model
- low power
- network design
- computational power
- activation function
- fpga device
- clock frequency
- hardware implementation
- real time
- connection weights
- biologically plausible
- real time image processing
- fpga implementation
- low cost
- single chip
- field programmable gate array
- signal processing
- hardware architecture