A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology.

Debabrata Ghosh S. K. Nandy

Published in: ICCD (1993)

Keyphrases

cmos technology
spl times
low power
low voltage
parallel processing
flip flops
power consumption
random access memory
low cost
floating point
data flow
power dissipation
image sensor
high speed
hardware implementation
pattern recognition
instruction set architecture
mixed signal
parallel architecture
digital images