Leakage Current Estimation of CMOS Circuit with Stack Effect.

Yongjun Xu Zuying Luo Xiaowei Li Li-Jian Li Xianlong Hong

Published in: J. Comput. Sci. Technol. (2004)

Keyphrases

low voltage
leakage current
circuit design
cmos technology
power line
design considerations
analog vlsi
high speed
delay insensitive
low cost
vlsi circuits
power consumption
power management
image sequences
low power