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An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators.

Jaime Ramírez-AnguloLalitha Mohana Kalyani-GarimellaAnnajirao GarimellaSri Raga Sudha GarimellaAntonio J. López-MartínRamón González Carvajal
Published in: VLSI Design (2008)
Keyphrases
  • low voltage
  • high speed
  • cmos technology
  • design considerations
  • low power
  • power line
  • random access memory
  • low cost
  • circuit design
  • image processing
  • multi view
  • cost effective
  • parallel processing