A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction.
Long ChenXiyuan TangArindam SanyalYeonam YoonJie CongNan SunPublished in: IEEE J. Solid State Circuits (2017)
Keyphrases
- noise reduction
- statistical estimation
- low power
- speckle noise
- single chip
- low cost
- power consumption
- high speed
- synthetic aperture radar
- edge preserving
- multiplicative noise
- sar images
- signal to noise ratio
- analog to digital converter
- edge detection
- wide dynamic range
- noise level
- median filter
- vlsi circuits
- noisy environments
- vlsi architecture
- image reconstruction
- image sensor
- digital signal processing
- low power consumption
- image segmentation
- mixed signal
- speech enhancement
- logic circuits
- cmos technology
- pattern recognition
- power reduction