TC: Throughput centric successive cancellation decoder hardware implementation for polar codes.
Tiben CheJingwei XuGwan S. ChoiPublished in: ICASSP (2016)
Keyphrases
- hardware implementation
- fpga implementation
- reed solomon
- error control
- decoding algorithm
- error correction
- joint source channel
- efficient implementation
- signal processing
- response time
- low density parity check
- software implementation
- hardware design
- ldpc codes
- turbo codes
- rotation invariant
- field programmable gate array
- dedicated hardware
- pipeline architecture
- image processing algorithms
- hardware architecture
- error concealment
- parallel architecture
- low complexity
- coding scheme
- rate compatible punctured convolutional
- real time
- distributed video coding
- image processing
- computer vision
- error detection
- message passing
- general purpose processors