Hardware architecture for lowering the error floor of LTE turbo codes.
Thibaud TonnellierCamille LerouxBertrand Le GalChristophe JégoBenjamin GadatNicolas Van WambekePublished in: DASIP (2016)
Keyphrases
- hardware architecture
- turbo codes
- hardware implementation
- error correction
- channel coding
- distributed video coding
- scalable video
- computer vision
- compressed images
- quality of service
- field programmable gate array
- associative memory
- video codec
- video streaming
- error propagation
- pattern recognition
- wireless channels
- motion estimation
- neural network