A novel hybrid memory architecture with parallel DRAM for fast packet buffers.
Arthur MutterPublished in: HPSR (2010)
Keyphrases
- processing elements
- level parallelism
- main memory
- memory subsystem
- multi processor
- distributed processing
- parallel hardware
- multithreading
- master slave
- packet switching
- buffer size
- hardware architecture
- parallel computers
- embedded dram
- management system
- memory access
- gigabit ethernet
- memory management
- real time
- dynamic random access memory
- high density
- processing units
- parallel processing
- hardware implementation
- packet loss
- memory bandwidth
- shared memory
- memory hierarchy
- parallel computing
- massively parallel
- parallel implementation
- low voltage
- multi core processors
- ibm zenterprise
- random access
- parallel architecture
- memory requirements
- pipelined architecture
- input output
- content addressable memory
- data structure