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A Low-Noise Design Technique for High-Speed CMOS Optical Receivers.

Dan LiGabriele MinoiaMatteo RepossiDaniele BaldiEnrico TemporitiAndrea MazzantiFrancesco Svelto
Published in: IEEE J. Solid State Circuits (2014)
Keyphrases
  • high speed
  • low power
  • real time
  • circuit design
  • neural network
  • low cost
  • design process
  • noisy data
  • single chip
  • case study
  • user interface
  • power consumption
  • frame rate
  • design methodology
  • high noise