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The Chip is Ready. Am I done? On-chip Verification using Assertion Processors.
José Augusto Miranda Nacif
Flávio Miana de Paula
Harry Foster
Claudionor José Nunes Coelho Jr.
Antônio Otávio Fernandes
Published in:
VLSI-SOC (2003)
Keyphrases
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low cost
functional verification
high speed
analog vlsi
signal processor
multithreading
high density
programmable logic
physical design
vlsi implementation
single chip
level parallelism
signal processing
parallel computation
circuit design
formal verification
evolvable hardware
low power
evolutionary algorithm