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A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors.
Chua-Chin Wang
Gang-Neng Sung
Chi-Chun Huang
Ching-Li Lee
Tian-Hau Chen
Wun-Ji Lin
Ron Hu
Published in:
J. Circuits Syst. Comput. (2008)
Keyphrases
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power consumption
low power
access control
high density
data transmission
cmos technology
end to end delay
remote access
machine learning
database systems
high speed
circuit design
network simulator