Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology.
Yongqing RenHong AnMing CongGuang XuLi WangPublished in: CSO (1) (2009)
Keyphrases
- network topology
- single chip
- high speed
- processor core
- ibm power processor
- functional verification
- multi core processors
- ad hoc networks
- network structure
- chip design
- functional units
- network topologies
- ibm zenterprise
- level parallelism
- parallel architectures
- multithreading
- random access memory
- routing protocol
- low power
- memory management
- memory subsystem
- instruction set
- mobile ad hoc networks
- overlay network
- protein protein interactions
- parallel processing
- energy conservation
- camera network
- computer architecture
- memory bandwidth