A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.
Kuan-Yueh James ShenSyed Feruz Syed FarooqYongping FanKhoa Minh NguyenQi WangMark NeidengardNasser A. KurdAmr ElshazlyPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
- low power
- mixed signal
- cmos technology
- vlsi architecture
- power consumption
- low cost
- signal processor
- high speed
- nm technology
- vlsi circuits
- single chip
- power reduction
- cmos image sensor
- image sensor
- high power
- wireless transmission
- low power consumption
- digital signal processing
- low voltage
- wide dynamic range
- logic circuits
- parallel algorithm
- power dissipation
- parallel processing
- focal plane
- delay insensitive
- power management
- multi channel
- signal processing
- analog to digital converter
- silicon on insulator