A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique.
Xiang ZhengMing LiuHong ChenHuamin CaoCong WangZhiqiang GaoPublished in: DDECS (2012)
Keyphrases
- cmos technology
- power consumption
- low power
- image sensor
- nm technology
- low voltage
- random access memory
- leakage current
- knowledge base
- silicon on insulator
- sensor networks
- real time
- power reduction
- low cost
- dynamic random access memory
- design considerations
- power management
- power dissipation
- parallel processing
- high speed
- power supply
- imaging systems
- data acquisition
- embedded dram
- video camera
- metal oxide semiconductor
- data sets
- digital camera
- x ray