A chip-stacked memory for on-chip SRAM-rich SoCs and processors.
Hideaki SaitoMasayuki NakajimaTakumi OkamotoYusuke YamadaAkira OhuchiNoriyuki IguchiToshitsugu SakamotoKoichi YamaguchiMasayuki MizunoPublished in: ISSCC (2009)
Keyphrases
- random access memory
- memory subsystem
- multithreading
- high speed
- memory access
- low cost
- processor core
- dynamic random access memory
- high density
- single chip
- level parallelism
- analog vlsi
- low power
- programmable logic
- signal processor
- memory bandwidth
- vlsi implementation
- low voltage
- power consumption
- embedded dram
- physical design
- parallel algorithm
- cmos technology
- memory requirements
- parallel processing
- parallel programming
- design considerations
- data transmission