An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design.
Yi-Jong YehSy-Yen KuoPublished in: J. Circuits Syst. Comput. (2002)
Keyphrases
- low power
- mixed signal
- single chip
- power consumption
- low cost
- vlsi circuits
- high speed
- low power consumption
- cmos image sensor
- cmos technology
- vlsi architecture
- ultra low power
- logic circuits
- analog to digital converter
- power dissipation
- digital signal processing
- low voltage
- energy dissipation
- multi channel
- high power
- digital circuits
- gate array
- nm technology
- circuit design
- power reduction
- delay insensitive
- wireless transmission
- vlsi implementation
- power supply
- power management
- image sensor
- digital camera
- design process
- wide dynamic range
- real time