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Test set embedding for deterministic BIST using a reconfigurable interconnection network.

Lei LiKrishnendu Chakrabarty
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2004)
Keyphrases
  • test set
  • interconnection networks
  • fault tolerant
  • parallel algorithm
  • multistage
  • routing algorithm
  • error rate
  • message passing
  • training set
  • test data
  • parallel computers
  • training data
  • distributed systems
  • graph cuts