Login / Signup
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
Alexandre M. Amory
Kees Goossens
Erik Jan Marinissen
Marcelo Lubaszewski
Fernando Moraes
Published in:
IET Comput. Digit. Tech. (2007)
Keyphrases
</>
high speed
power dissipation
design process
object oriented
low cost
data management
parallel processing
low power