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Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology.
Jaesik Lee
Yoonjong Huh
Peter Bendix
Sung-Mo Kang
Published in:
ISCAS (4) (2001)
Keyphrases
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high frequency
cmos technology
low power
mixed signal
low frequency
power dissipation
visual quality
power consumption
wavelet transform
high speed
high resolution
subband
digital circuits
low voltage
user interface
low cost
wavelet coefficients
image sequences
parallel processing
multi channel
design process