A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.
Sara ChoiHong Keun AhnByungkyu SongJung Pill KimSeung-Hyuk KangSeong-Ook JungPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2019)
Keyphrases
- low power
- reed solomon
- low density parity check
- ldpc codes
- error correction
- decoding algorithm
- low cost
- high speed
- error control
- power consumption
- low power consumption
- channel coding
- message passing
- single chip
- distributed video coding
- joint source channel
- logic circuits
- vlsi architecture
- decoding process
- physical layer
- turbo codes
- image transmission
- error correcting
- rate allocation
- low complexity
- unequal error protection
- error detection
- coding scheme