Clock Jitter Compensation in High-Rate ADC Circuits.
Zaid J. TowficShang-Kee TingAli H. SayedPublished in: IEEE Trans. Signal Process. (2012)
Keyphrases
- high rate
- high speed
- low rate
- false alarms
- power consumption
- packet loss
- delay insensitive
- analog vlsi
- logic synthesis
- false negative
- asynchronous circuits
- power dissipation
- analog circuits
- computer vision
- logic circuits
- digital circuits
- circuit design
- false positives
- power reduction
- low cost
- object recognition
- machine learning
- duty cycle