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Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor.
Ravinder Rachala
Miguel Rodriguez
Stephen Kosonocky
Milos Trajkovic
Published in:
ISLPED (2016)
Keyphrases
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graphics processing units
highly parallel
power system
circuit design
random access memory
efficient implementation
computer architecture
computation intensive
embedded dram
operating system
memory management
low overhead
instruction set
bit parallel
metal oxide
cell broadband engine architecture