Login / Signup
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.
Liangxiao Tang
Weixin Gai
Linqi Shi
Xiao Xiang
Kai Sheng
Ai He
Published in:
ISSCC (2018)
Keyphrases
</>
power consumption
power supply
high speed
clock gating
low power
single phase
nm technology
cmos technology
low voltage
hd video
adaptive threshold
power reduction
metal oxide
duty cycle
power management
communication systems
power dissipation
low cost
intelligent control
transmission line