Login / Signup
A Low Voltage 6T SRAM Cell Design and Analysis Using Cadence 90nm And 45nm CMOS Technology.
T. Kalpana
Challa Lakshmi Reddy
Bandaru Saranya
Poluboyina Naveen
Published in:
ICDCS (2024)
Keyphrases
</>
cmos technology
low voltage
low power
power consumption
power dissipation
parallel processing
high speed
leakage current
image sensor
power line
random access memory
mixed signal
silicon on insulator
low cost
real time
design considerations
multimedia
edge detection
computer vision